Lead ASIC DFT Engineer

, and fault coverage closure for complex silicon issues. Develop and validate DFT constraints, including DFT SDC, timing checks... and fault coverage debug. DFT RTL, DFD, DFT verification, and IP-level DFT integration. DFT SDC creation and DFT timing...

Lugar: San Jose, CA | 28/03/2026 19:03:41 PM | Salario: S/. No Especificado | Empresa: Cyient

Integration RTL Design Engineer

validation. Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform static timing analysis (STA... → Synthesis → STA → Physical Design → Tape-out Experience writing and debugging SDC timing constraints, including multi-cycle...

Lugar: San Jose, CA | 27/03/2026 22:03:35 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Service Lot Porter

Development Center (SDC) dedicated to setting and reminding customers of their service appointments. We have extremely...

Lugar: National City, CA | 27/03/2026 18:03:20 PM | Salario: S/. No Especificado | Empresa: Dalton Motors

Rental Management Trainee

for in Transportation – Women in Trucking Overdrive Award – General Motors Food Logistics’ Top 3PL Award – SDC EXEC Reader’s Choice...

Lugar: Woodinville, WA | 27/03/2026 18:03:08 PM | Salario: S/. No Especificado | Empresa: Ryder