Director Applications Engineering

structured debug and resolution plans in partnership with R&D, Product, and Program teams. Define and standardize best practices...: Front-End (RTL/SystemVerilog, CDC/RDC, lint, verification) and/or Back-End (synthesis, STA, place & route, signoff...

Lugar: Sunnyvale, CA | 05/05/2026 22:05:13 PM | Salario: S/. No Especificado | Empresa: Synopsys

Digital ASIC Design Manager

ASIC R&D Manager to lead and grow this capability within our ASIC team. The role is based in Colorado Springs at the foot...-architecture and implementation (SystemVerilog/Verilog/VHDL), synthesis, STA/timing closure, and power/performance optimization...

Lugar: Colorado Springs, CO | 02/05/2026 23:05:12 PM | Salario: S/. No Especificado | Empresa: Keysight Technologies

ASIC Physical Design Manager

. We are seeking an ASIC Physical Design R&D Manager to lead our ASIC Physical Design team—overseeing end-to-end physical... verification and signoff (DRC/LVS, STA, power/IR/EM, reliability as applicable) and drive tape release readiness with clear signoff...

Lugar: Colorado Springs, CO | 02/05/2026 20:05:34 PM | Salario: S/. No Especificado | Empresa: Keysight Technologies

ASIC Digital Physical Design Manager

products. We are seeking an ASIC Physical Design R&D Manager to lead our ASIC Physical Design team—overseeing end-to-end... enablement for predictability and quality. Lead physical verification and signoff (DRC/LVS, STA, power/IR/EM, reliability...

Lugar: Colorado Springs, CO | 01/05/2026 17:05:27 PM | Salario: S/. No Especificado | Empresa: Keysight Technologies

Digital ASIC Design Manager

. We are seeking a Digital Design ASIC R&D Manager to lead and grow this capability within our ASIC team. The role is based... preferred). Strong hands-on depth in RTL micro-architecture and implementation (SystemVerilog/Verilog/VHDL), synthesis, STA...

Lugar: Colorado Springs, CO | 01/05/2026 17:05:07 PM | Salario: S/. No Especificado | Empresa: Keysight Technologies

Silicon Design Engineer

with digital P&R design flow, RTL coding (Verilog/System Verilog) and design verification (Design Compiler, STA, SVA, UVM...) to generate optimized netlists. Lead Static Timing Analysis (STA) runs using e.g. PrimeTime to validate setup/hold margins...

Lugar: San Jose, CA | 30/04/2026 22:04:03 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Applications Engineering, Sr Staff Engineer

to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow... everyone else a headache. You have spent years elbows-deep in VLSI design, not just writing RTL but getting it to synthesis, through STA...

Lugar: Sunnyvale, CA | 30/04/2026 20:04:58 PM | Salario: S/. No Especificado | Empresa: Synopsys