CPU Server Physical Design Clock Engineer

Summary: As a Physical Design Clock Engineer, you will work with microarchitecture, RTL design, CAD, block level and top... in clock H-tree, mesh, spines and CTS implementations. Good understanding of device physics, RC delay and electrical aspects...

Lugar: Austin, TX | 03/03/2026 03:03:55 AM | Salario: S/. $148300 - 222500 per year | Empresa: Qualcomm

Member of Technical Staff (Storage)

, and is responsible for the safe, durable and efficient persistence and retrieval of data, on top of which the rest of the database... is built. Our team develops and maintains Pebble, an innovative Log Structured Merge (LSM) Tree storage engine, purpose built...

Lugar: New York City, NY | 28/02/2026 19:02:18 PM | Salario: S/. $185000 - 200000 per year | Empresa: Cockroach Labs

Director, Corporate Communications & Public Relations

devices and smart home products, consistently ranked as the world’s top provider of Wi-Fi devices. The company is committed..., including innovation, economic contribution, sustainability, and community initiatives (e.g., tree planting, giving programs...

Lugar: Irvine, CA | 30/04/2026 17:04:10 PM | Salario: S/. $175000 - 200000 per year | Empresa: TP-Link

Directed Energy Systems Safety Lead

including: Conducting analyses like Functional Hazard Analysis (FHA), Fault Tree Analysis (FTA), and Preliminary Hazard... DoD Top Secret security clearance. Clearance Level Secret The salary range for this role...

Lugar: Albuquerque, NM | 20/05/2026 19:05:36 PM | Salario: S/. $139371 - 197400 per year | Empresa: AeroVironment

Senior Product Quality Engineer

sigma, Fault tree analysis, and DMAIC methodologies. Working knowledge of design review and quality management of PCBA... offers;and are considered part of Anduril's total compensation package. Additionally, Anduril offers top-tier benefits for full-time employees...

Lugar: Costa Mesa, CA | 16/04/2026 23:04:57 PM | Salario: S/. $146000 - 194000 per year | Empresa: Anduril Industries

ASIC Implementation Engineer

methods and strategies;preferable in-depth experience in top-level STA EM/IR Analysis, Place and Route Clock Tree...;preferable in-depth experience in top-level floorplanning Flow and Methodology Development Collaborating with IC Design RTL...

Lugar: San Jose, CA | 28/04/2026 21:04:27 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Physical Design Engineer

Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division... aspects of taking RTL to silicon tapeout. Responsibilities: Own chip floor planning, partition creation, clock tree...

Lugar: San Jose, CA | 10/04/2026 00:04:45 AM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom