Senior Principal Engineer, Micro-architecture and RTL

Principal Engineer with Marvell, you’ll be a member of the Central Engineering's connectivity business group. This team hires... specifications. System Verilog RTL coding with System Verilog Assertions. Universal Verification Methodology. Creating modular...

Lugar: Santa Clara, CA | 29/05/2026 22:05:29 PM | Salario: S/. No Especificado | Empresa: Marvell

Digital Verification Engineer I

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology... provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications...

Lugar: Austin, TX | 22/05/2026 00:05:38 AM | Salario: S/. $84000 - 156000 per year | Empresa: Silicon Labs

FPGA Development Intern (Fall 2026 - 4-8 months)

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy... verification using Universal Verification Methodology (UVM). Technical documentation writing and datasheet analysis. The life...

Lugar: Atlanta, GA | 17/05/2026 02:05:53 AM | Salario: S/. No Especificado | Empresa: Ciena

Application Security Intern

our universal token vault into their technology stack to manage the complexities of payment data tokenization across processors... revenue and business opportunities. VGS provides processor-agnostic tokenization solutions via secure universal token vaults...

Lugar: USA | 18/04/2026 01:04:54 AM | Salario: S/. $20 per hour | Empresa: Very Good Security
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