FPGA Test Engineer (m/w/d)

gezielter RTL-Simulationstests, um die Funktionalität komplexer FPGA-Designs sicherzustellen, gehört ebenfalls zu deinen... du die RTL-Simulationsverifikation souverän gegenüber Kunden und Behörden Zudem testet du technische Anforderungen...

Lugar: Lindenberg im Allgäu, Bayern | 13/01/2026 03:01:31 AM | Salario: S/. €58000 - 65000 per year | Empresa: Ferchau Engineering

Operations Manager (m/f/x) 1

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Lugar: Mörfelden-Walldorf, Hessen | 01/04/2026 01:04:41 AM | Salario: S/. No Especificado | Empresa: RTL

Senior Sales Manager (m/f/d) Debt Collection

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Lugar: Berlin | 13/03/2026 22:03:26 PM | Salario: S/. No Especificado | Empresa: RTL

Senior Digital ASIC Design Engineer (m/f/d)

Architecture development for CMOS IP designs Design and RTL coding of digital and full-custom modules Verification on module... Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs...

Lugar: Deutschland | 07/04/2026 23:04:29 PM | Salario: S/. No Especificado | Empresa: Advantest

Expert Digital ASIC Design Engineer (m/f/d)

& Responsibilities Requirements gathering and elicitation for devices and IP Architecture development for CMOS designs Design and RTL... in digital design (SOC), ASIC design methodologies and silicon development cycle Experience in Register Transfer Level (RTL...

Lugar: Deutschland | 07/04/2026 23:04:29 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior Digital ASIC Design Engineer (m/f/d)

and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/cases generation... (ASIC) design methodologies and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog...

Lugar: Deutschland | 07/04/2026 21:04:02 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior Digital ASIC Design Engineer Synthesis (m/f/d)

& Responsibilities Architecture development for CMOS designs Design and RTL coding of digital and full-custom modules Verification... cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard simulation...

Lugar: Deutschland | 07/04/2026 18:04:31 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior Digital ASIC Design Engineer (m/f/d)

Architecture development for CMOS IP designs Design and RTL coding of digital and full-custom modules Verification on module... Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs...

Lugar: Deutschland | 07/04/2026 18:04:38 PM | Salario: S/. No Especificado | Empresa: Advantest