FPGA Design Engineer - Vivado Expert

and RTL designs using Vivado. Capture and analyze screenshots with more than 2.5 megapixels using either a high-resolution...

Lugar: Berlin | 15/09/2026 17:09:06 PM | Salario: S/. No Especificado | Empresa: Mercor

Senior Engineer Digital IP (f/m/div)

. Are you in? Your role Key responsibilities in your new role Hands-on digital IP design execution, RTL implementation, design documentation..., integration support, and release readiness. Develop high-quality RTL in System Verilog/Verilog for reusable, configurable...

Lugar: Dresden, Sachsen | 08/09/2026 19:09:05 PM | Salario: S/. No Especificado | Empresa: Infineon

Senior Engineer Digital IP (f/m/div)

. Are you in? Your role Key responsibilities in your new role Hands-on digital IP design execution, RTL implementation, design documentation..., integration support, and release readiness. Develop high-quality RTL in System Verilog/Verilog for reusable, configurable...

Lugar: Dresden, Sachsen | 01/09/2026 20:09:57 PM | Salario: S/. No Especificado | Empresa: Infineon

PCIE SOC Application Engineer (Sr Staff)

issues related to RTL simulation, synthesis, floorplanning, timing closure, and silicon/system bring-up. Supporting silicon... and academic background considered). Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis...

Lugar: München, Bayern | 22/08/2026 00:08:36 AM | Salario: S/. No Especificado | Empresa: Synopsys
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