Senior Digital IP Verification Engineer (f/m/d)

. Architect, develop, debug, and maintain UVM-based verification environments for RTL simulation. Develop testcases... across multiple abstraction levels (RTL, power-aware RTL, gate-level, FPGA, and emulation platforms). Execute regressions, analyze...

Lugar: München, Bayern | 13/08/2026 22:08:13 PM | Salario: S/. No Especificado | Empresa: NXP Semiconductors

FPGA Development / System Integration Engineer (f/m/d)

of RTL level designs for blocks/sub-systems/FPGAs from high-level requirements Take ownership of blocks/sub-systems/FPGA... of implementing and debugging complex RTL designs Hands on experience of electronics system integration of FPGA/ASIC based functions...

Lugar: Hamburg | 11/08/2026 20:08:06 PM | Salario: S/. No Especificado | Empresa: Universal Quantum