Front-End & Back-End SoC Engineering, Principal Engineer

integration and hardening (PCIe, DDR, UCIe, Ethernet), RTL development, functional verification planning, and DFT implementation.... Deep knowledge of SoC architecture and integration, RTL design in Verilog/SystemVerilog, functional verification, DFT...

Lugar: München, Bayern | 21/07/2026 17:07:08 PM | Salario: S/. No Especificado | Empresa: Synopsys

IC Digital Design Technical Lead

and implement complex digital systems (MCU, DSP, accelerators) Strong RTL design skills with production‑quality IP Solid... of semiconductor design experience Strong RTL design skills (Verilog/SystemVerilog) Experience with MCU/DSP systems and digital IP...

Lugar: Bayern | 16/07/2026 17:07:57 PM | Salario: S/. No Especificado | Empresa: Michael Page

C++ Engineer (f/m/d)

possible), mobility (Germany ticket & JobRad), sports & health offerings, mental health support, corporate benefits, RTL+ access...

Lugar: Berlin | 16/07/2026 02:07:50 AM | Salario: S/. No Especificado | Empresa: Penguin Books