Senior Digital ASIC Design Engineer Synthesis (m/f/d)

and at scale. Job Duties & Responsibilities Architecture development for CMOS designs Design and RTL coding of digital and full... development cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard...

Lugar: Baden-Württemberg | 25/08/2026 17:08:44 PM | Salario: S/. No Especificado | Empresa: Advantest

Digital ASIC Design Engineer (m/f/d)

Architecture development for CMOS IP designs Design and RTL coding of digital and full-custom modules Verification on module... in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs Basic knowledge...

Lugar: Baden-Württemberg | 25/08/2026 17:08:52 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior Digital ASIC Design Engineer (m/f/d)

Architecture development for CMOS IP designs Design and RTL coding of digital and full-custom modules Verification on module... in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs Basic knowledge...

Lugar: Baden-Württemberg | 25/08/2026 17:08:41 PM | Salario: S/. No Especificado | Empresa: Advantest

PCIE SOC Application Engineer (Sr Staff)

issues related to RTL simulation, synthesis, floorplanning, timing closure, and silicon/system bring-up. Supporting silicon... and academic background considered). Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis...

Lugar: München, Bayern | 21/08/2026 19:08:16 PM | Salario: S/. No Especificado | Empresa: Synopsys