Senior Digital ASIC Design Engineer (m/f/d)

and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/cases generation... (ASIC) design methodologies and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog...

Lugar: Deutschland | 07/04/2026 18:04:20 PM | Salario: S/. No Especificado | Empresa: Advantest

FPGA Design Engineer (m/f/d)

families and IP for timing‑critical and safety‑related functions. Develop synthesizable RTL (VHDL) for: PWM generators... and a solid understanding of synthesizable RTL design, timing constraints, and clock domain crossing techniques. Hands...

Lugar: Berlin | 04/04/2026 01:04:52 AM | Salario: S/. No Especificado | Empresa: GE Vernova

DevOps Engineer (w/m/d) - Google Cloud Platform

-Entwicklungseinheit der RTL Group – Europas führender Free-TV Sendergruppe. Unsere proprietäre Werbetechnologie ist auf die spezifischen.... Die Media Sales Division von smartclip wird mit RTL AdConnect und G&J iMS zu einem internationalen Advertising Sales Champion...

Lugar: Hamburg | 03/04/2026 17:04:19 PM | Salario: S/. No Especificado | Empresa: Smartclip

Senior ASIC Design Engineer DfT (m/f/d)

designs Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan... of digital, mixed signal, RF and power device test methodologies Experience in Register Transfer Level (RTL) coding (Verilog...

Lugar: Deutschland | 31/03/2026 20:03:54 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior Digital ASIC Design Engineer Verification (m/f/d)

Architecture development for CMOS designs Design and RTL coding of digital and full-custom modules Verification on module... Transfer Level (RTL) coding (Verilog and System-Verilog) Experience with verification methodologies and concepts Experience...

Lugar: Deutschland | 31/03/2026 20:03:42 PM | Salario: S/. No Especificado | Empresa: Advantest

Digital Physical Design Engineer

, you will participate in the physical implementation flow for complete MCU SoCs. Your responsibilities will include: Performing RTL-to-gate... team and proposing RTL improvements for timing critical paths Running Static Timing Analysis (STA) and closing timing...

Lugar: Deutschland | 28/03/2026 03:03:58 AM | Salario: S/. No Especificado | Empresa: European Recruitment