Senior Digital IC Design Engineer

cycle, from specification and RTL design through functional and physical verification, all the way to post‑silicon... between digital logic and analog/mixed‑signal blocks. Experience with full design flow: architecture, RTL design, synthesis...

Lugar: Dresden, Sachsen | 25/04/2026 17:04:40 PM | Salario: S/. No Especificado | Empresa: Ferroelectric Memory

IC Digital Design Technical Lead

complex digital systems (MCU, DSP, accelerators) Strong RTL design skills with production‑quality IP Solid understanding... of semiconductor design experience Strong RTL design skills (Verilog/SystemVerilog) Experience with MCU/DSP systems and digital IP...

Lugar: München, Bayern | 17/04/2026 17:04:21 PM | Salario: S/. €115842 - 173763 per year | Empresa: Michael Page

Senior Software Engineer API - Node.js, SQL

– fast, hands-on, and without unnecessary meeting overhead. smartclip is the adtech development unit of RTL Group — Europe... of smartclip will merge with RTL AdConnect and G&J iMS to form RTL AdAlliance, an international advertising and technology sales...

Lugar: Hamburg | 16/04/2026 17:04:38 PM | Salario: S/. No Especificado | Empresa: Smartclip

Expert Digital ASIC Design Engineer (m/f/d)

& Responsibilities Requirements gathering and elicitation for devices and IP Architecture development for CMOS designs Design and RTL... in digital design (SOC), ASIC design methodologies and silicon development cycle Experience in Register Transfer Level (RTL...

Lugar: Deutschland | 08/04/2026 01:04:56 AM | Salario: S/. No Especificado | Empresa: Advantest

Senior Digital ASIC Design Engineer Synthesis (m/f/d)

& Responsibilities Architecture development for CMOS designs Design and RTL coding of digital and full-custom modules Verification... cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard simulation...

Lugar: Deutschland | 08/04/2026 01:04:37 AM | Salario: S/. No Especificado | Empresa: Advantest

Senior Digital ASIC Design Engineer (m/f/d)

Architecture development for CMOS IP designs Design and RTL coding of digital and full-custom modules Verification on module... Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs...

Lugar: Deutschland | 07/04/2026 23:04:54 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior Digital ASIC Design Engineer (m/f/d)

Architecture development for CMOS IP designs Design and RTL coding of digital and full-custom modules Verification on module... Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs...

Lugar: Deutschland | 07/04/2026 23:04:53 PM | Salario: S/. No Especificado | Empresa: Advantest