FPGA Design Engineer (m/f/d)

families and IP for timing‑critical and safety‑related functions. Develop synthesizable RTL (VHDL) for: PWM generators... and a solid understanding of synthesizable RTL design, timing constraints, and clock domain crossing techniques. Hands...

Lugar: Berlin | 04/04/2026 00:04:45 AM | Salario: S/. No Especificado | Empresa: GE Vernova

DevOps Engineer (w/m/d) - Google Cloud Platform

-Entwicklungseinheit der RTL Group – Europas führender Free-TV Sendergruppe. Unsere proprietäre Werbetechnologie ist auf die spezifischen.... Die Media Sales Division von smartclip wird mit RTL AdConnect und G&J iMS zu einem internationalen Advertising Sales Champion...

Lugar: Hamburg | 03/04/2026 17:04:48 PM | Salario: S/. No Especificado | Empresa: Smartclip

Digital Design Engineer (f/m/div)

. Are you in? Your Role Key responsibilities in your new role Design, code in RTL, synthesize and integrate complex digital blocks... years of experience in digital design, with a focus on automotive or safety-critical systems Proficiency in RTL coding...

Lugar: München, Bayern | 03/04/2026 01:04:08 AM | Salario: S/. No Especificado | Empresa: Infineon

Senior Digital ASIC Design Engineer (m/f/d)

Architecture development for CMOS IP designs Design and RTL coding of digital and full-custom modules Verification on module... Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs...

Lugar: Deutschland | 03/04/2026 01:04:57 AM | Salario: S/. No Especificado | Empresa: Advantest