Junior Digital Circuit Designer

www.gf.com. Your Job Design and implement digital logic blocks (RTL) using Verilog/SystemVerilog. Integrate digital.... Analyze design behavior and resolve RTL issues. Support synthesis, timing analysis, and implementation tasks. Participate...

Lugar: Dresden, Sachsen | 25/01/2026 03:01:48 AM | Salario: S/. No Especificado | Empresa: GlobalFoundries

FPGA Design Engineer (m/f/d)

families and IP for timing‑critical and safety‑related functions. Develop synthesizable RTL (VHDL) for: PWM generators... and a solid understanding of synthesizable RTL design, timing constraints, and clock domain crossing techniques. Hands...

Lugar: Berlin | 17/01/2026 03:01:03 AM | Salario: S/. No Especificado | Empresa: GE Vernova