Senior Digital ASIC Design Engineer Verification (m/f/d)

Architecture development for CMOS designs Design and RTL coding of digital and full-custom modules Verification on module... Transfer Level (RTL) coding (Verilog and System-Verilog) Experience with verification methodologies and concepts Experience...

Lugar: Deutschland | 31/03/2026 23:03:52 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior ASIC Design Engineer DfT (m/f/d)

designs Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan... of digital, mixed signal, RF and power device test methodologies Experience in Register Transfer Level (RTL) coding (Verilog...

Lugar: Deutschland | 31/03/2026 22:03:00 PM | Salario: S/. No Especificado | Empresa: Advantest

Digital Physical Design Engineer

, you will participate in the physical implementation flow for complete MCU SoCs. Your responsibilities will include: Performing RTL-to-gate... team and proposing RTL improvements for timing critical paths Running Static Timing Analysis (STA) and closing timing...

Lugar: Deutschland | 28/03/2026 02:03:11 AM | Salario: S/. No Especificado | Empresa: European Recruitment