Verification Engineer
by property-based test generation rather than fixed directed vectors.Write SystemVerilog Assertions (SVA) to catch protocol... both SVA and native SystemVerilog covergroups. If you have opinions on how verification should be done, there’s real room...
Lugar: Karlsruhe, Baden-Württemberg | 21/10/2026 17:10:49 PM | Salario: S/. No Especificado | Empresa: Ubitium GmbH