Low Power Design Engineer
, power aware DV and high speed clocking desired. Proficiency in Verilog/System Verilog coding, verification techniques...
Lugar: Tijuana, B.C. | 07/02/2026 22:02:50 PM | Salario: S/. No Especificado | Empresa: NAPS
HIL/SIL Integration and Deployment Engineer
, and powertrain subsystems with the goal of improving the Design Verification (DV) efficiency and reducing the testing time...
Lugar: Naucalpan de Juárez, Méx. | 04/02/2026 23:02:18 PM | Salario: S/. No Especificado | Empresa: Ford