Soc/Ip Design Verification Engineer

. You will own verification planning, UVM testbench development, test content creation (directed and constrained-random), coverage..., and signoff.* Architect and implement UVM environments (agents, drivers, monitors, sequencers, scoreboards, reference models...

Lugar: Jalisco | 06/06/2026 17:06:50 PM | Salario: S/. No Especificado | Empresa: Intel

Design Verification Engineer

, PRIMESIM. - Basic understanding on digital simulators, such as Verilog and UVM Methodology (or equivalent). - Good...

Lugar: Jalisco | 06/06/2026 17:06:26 PM | Salario: S/. No Especificado | Empresa: Micron