environments. Experience with board, processor, or ASIC bring-up. Experience with DDR, SPI, eSPI, I2C, LPC, and PCIe. Experience...
relevant to the ASIC development process including Verilog, VHDL, Unix/Perl Scripting or Python, and C. Experience with High...
ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're... engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment...
ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN ENGINEER II (SILICON ENGINEERING) At SpaceX we're... engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space...
ultimate goal of enabling human life on Mars. SR. SOC/ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging... engineering and ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in space...
engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment... pipeline planning and top level design for testability (DFT) planning Collaborate with chip architects, ASIC engineers...
ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN ENGINEER II (SILICON ENGINEERING) At SpaceX we're... engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space...
for the next generation of our ML ASIC. This is a fast-paced, intellectually challenging position, and you'll work...
ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging... engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space...
IP/ASIC design and Verilog RTL development Experience in full IP design cycle, requirements definition, architecture... and post silicon validation. Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects...