SSG Design Engineering Intern (Fall 2026)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design... Engineering Intern The Cadence Silicon Solutions Group (SSG) is seeing rapid adoption of our industry leading Digital IP...

Lugar: San Jose, CA | 17/07/2026 19:07:23 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems

Intern - Characterization and Support

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.... This is an on-site internship role in San Jose, California, within the Cadence DDR IP group for a Post-Silicon Validation Engineering...

Lugar: San Jose, CA | 13/06/2026 23:06:16 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems

Intern, Digital Design - Fall 2026

of FPGA systems using logic design and RTL coding. Lab Debug of FPGA prototypes using logic analyzers, oscilloscopes... electronics for the connected world smaller, thinner, faster and better. Job Summary This position is for a design...

Lugar: San Diego, CA | 12/08/2026 01:08:47 AM | Salario: S/. No Especificado | Empresa: Murata

Intern, Digital Design - Fall 2026

of FPGA systems using logic design and RTL coding. Lab Debug of FPGA prototypes using logic analyzers, oscilloscopes... electronics for the connected world smaller, thinner, faster and better. Job Summary This position is for a design...

Lugar: San Diego, CA | 11/08/2026 17:08:25 PM | Salario: S/. No Especificado | Empresa: Murata

IP & Design Engineering Intern (Fall 2026)

with RF/mm-Wave circuit design. Proficient with Cadence based EDA tools. Language Fluency - English (Written & Verbal... combination of design, development, and fabrication services to some of the world’s most inspired technology companies...

Lugar: Texas | 07/08/2026 22:08:16 PM | Salario: S/. No Especificado | Empresa: GlobalFoundries

Electrical Engineer III

, electrical safety, and regulatory standards such as IEC 60601. Experience with PCB design tools such as Altium, OrCAD, Cadence...Duration: 12+ months Contract Hybrid - Three days onsite Key Responsibilities Design, develop, and test...

Lugar: Marlborough, MA | 07/08/2026 19:08:21 PM | Salario: S/. No Especificado | Empresa: US Tech Solutions

Principal COE Digital Design Engineer

, and design sign-off flows Experience using industry-standard EDA tools from Synopsys, Cadence, Mentor/Siemens Proficient..., and knowledge across all business units to drive first-pass-right silicon. As part of the COE, you will design, verify...

Lugar: San Diego, CA | 06/08/2026 22:08:03 PM | Salario: S/. $160400 - 237320 per year | Empresa: Marvell

Senior Staff Design Engineer - Memory Subsystem COE

, and knowledge across all business units to drive first-pass-right silicon. As part of the COE, you will design, verify... customers — working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation...

Lugar: San Diego, CA | 06/08/2026 20:08:23 PM | Salario: S/. $135900 - 201130 per year | Empresa: Marvell

SI Interconnect Co-op

Your Job As an SI Interconnect Intern, you will work at the intersection of mechanical design and electrical... exposure to: Automotive high-speed links (Self-driving car data backbones). Automotive Ethernet, Ser, Deser and other systems...

Lugar: Rochester Hills, MI | 06/08/2026 17:08:41 PM | Salario: S/. No Especificado | Empresa: Molex

Tool Install Project Manager

and Installation up to Supplier Qualification;from Pre-Design through construction install to SL2SO Support the TIM and Functional... to drive decision making and change at the cadence Moore's law required Verbal and written communication skills, assertiveness...

Lugar: Phoenix, AZ | 06/08/2026 01:08:31 AM | Salario: S/. $83890 - 166800 per year | Empresa: Intel