Senior Staff Applications Engineer

a highly skilled and experienced Senior Staff Applications Engineer specializing in SerDes IP design and application. This role... in digital signal processing (DSP) algorithms, mixed-signal circuit design, bench debug, system application and customer support...

Lugar: Santa Clara, CA | 08/01/2026 01:01:20 AM | Salario: S/. $121400 - 181800 per year | Empresa: Marvell

Principal Applications Engineer

design and verification (e.g., Cadence, Synopsys). Experience with lab equipment for signal integrity analysis and debugging... circuit design. This role is critical in driving the successful integration and application of Marvell’s SerDes IP...

Lugar: Santa Clara, CA | 07/01/2026 18:01:58 PM | Salario: S/. $143200 - 214500 per year | Empresa: Marvell

Senior Layout Designer

Programming/scripting in C/C++, Python. UNIX/Linux operating systems. 8+ years of experience in layout design, Cadence Virtuoso... design platforms, and integrates components into hierarchical systems to provide deployment coverage for end-to-end EDA tool...

Lugar: Hillsboro, OR | 07/12/2025 00:12:44 AM | Salario: S/. No Especificado | Empresa: Intel

Systems Development Engineer II, AFSS

and drive product vision and lead the design of our systems. Key job responsibilities Primary responsibilities include... software, automation of support processes, documentation of our systems, manage AFSS org level operational cadence and programs...

Lugar: Seattle, WA | 06/12/2025 22:12:55 PM | Salario: S/. No Especificado | Empresa: Amazon

Bell Labs Platform&ASIC Research Intern

) Experience in ASIC physical design: circuit layout using Cadence (Innovus, Spectre, Virtuoso) and Synopsys (VCS, ICC) Knowledge... researchers on the design and development of ASIC and/or proof-of-concept system platform Participate in a research project, work...

Lugar: Murray Hill, NJ | 05/12/2025 22:12:43 PM | Salario: S/. No Especificado | Empresa: Nokia