Principal Physical Verification Engineer

/ERC/LUP/PERC results Experience with using either ICV or Calibre verification tools Understanding advance TSMC DRC rules... (ICV/Calibre) Able to assemble a flow to support block/chip level PV Strong expertise in: Floorplanning to avoid DRC...

Lugar: San Jose, CA | 25/09/2026 23:09:46 PM | Salario: S/. No Especificado | Empresa: Celero Communications, Inc.

Principal Physical Verification Engineer

/ERC/LUP/PERC results Experience with using either ICV or Calibre verification tools Understanding advance TSMC DRC rules... (ICV/Calibre) Able to assemble a flow to support block/chip level PV Strong expertise in: Floorplanning to avoid DRC...

Lugar: Irvine, CA | 25/09/2026 21:09:53 PM | Salario: S/. No Especificado | Empresa: Celero Communications, Inc.

Principal ASIC Design Engineer

) and physical verification sign-off (Mentor Calibre) — candidates with full front-to-back implementation experience are strongly...

Lugar: Boise, ID | 25/09/2026 19:09:20 PM | Salario: S/. No Especificado | Empresa: Micron

High-Speed Analog Layout Design Engineer

using industry-standard tools (Pegasus, Calibre, etc.) Contribute to chip-level planning including top-level floor planning..., and power/ground grid design Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools...

Lugar: Irvine, CA | 25/09/2026 00:09:47 AM | Salario: S/. No Especificado | Empresa: Celero Communications, Inc.