Senior / Lead Data Converter IC Design Engineer (FinFET)
constraints (fin quantization, degraded gm/gds, 3D RC extraction). EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX...
constraints (fin quantization, degraded gm/gds, 3D RC extraction). EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX...
constraints (fin quantization, degraded gm/gds, 3D RC extraction). EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX...
constraints (fin quantization, degraded gm/gds, 3D RC extraction). EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX...
constraints (fin quantization, degraded gm/gds, 3D RC extraction). EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX...
constraints (fin quantization, degraded gm/gds, 3D RC extraction). EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX...
constraints (fin quantization, degraded gm/gds, 3D RC extraction). EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX...
constraints (fin quantization, degraded gm/gds, 3D RC extraction). EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX...
constraints (fin quantization, degraded gm/gds, 3D RC extraction). EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX...
or parameterized cell (PCell) development. Experience with Calibre design rule checking (DRC) and layout versus schematic (LVS) flows...
constraints (fin quantization, degraded gm/gds, 3D RC extraction). EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX...