Principal Design-for-Test (DFT) Engineer
Principal DFT Engineer CeleroCommunications is seeking a talented DFT Engineer to join our silicon engineering...
Principal DFT Engineer CeleroCommunications is seeking a talented DFT Engineer to join our silicon engineering...
Lead/Principal Full-Chip Physical Verification Engineer Key Responsibilities Team & Project Leadership Lead full chip Physical Verification effort Own execution plans, schedules for full-chip Drive accountability for quality, mileston...
Lead/Principal Full-Chip Physical Verification Engineer Key Responsibilities Team & Project Leadership Lead full chip Physical Verification effort Own execution plans, schedules for full-chip Drive accountability for quality, mileston...
CeleroCommunications ( ) is building the next generation of intelligent optical connectivity for AI infrastructure. Founded...Director of Product Marketing – Coherent DSP & Optical Networking Location: Irvine, CA (HQ) or remote About Celero...
Senior/Principal High-Speed Analog Layout Design Engineer About the Role Celero Communication Inc. is an exciting... are valued The opportunity to grow alongside Celero as we scale and shape the future of our industry A foundational role...
Principal High-Speed Analog Layout Design Engineer About the Role Celero Communication Inc. is an exciting and fast... are valued The opportunity to grow alongside Celero as we scale and shape the future of our industry A foundational role...
Senior/Principal Physical Design Engineer Core Responsibilities RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. Design Optimization: Manage floor-planning, bump planning, power g...
CeleroCommunications ( ) is building the next generation of intelligent optical connectivity for AI infrastructure. Founded...Director of Product Marketing – Coherent DSP & Optical Networking Location: San Jose, CA or remote About Celero...
Senior/Principal Physical Design Engineer Core Responsibilities RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. Design Optimization: Manage floor-planning, bump planning, power g...
Principal SerDes Design Engineer About the job We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI. Candidate will have the...