Principal/ Senior Principal Digital ASIC Circuit Design Engineer

VCS - Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler - Static Timing – Synopsys Primetime..., Cadence Genus or Cadence RTL Compiler - Static Timing – Synopsys Primetime or Cadence Tempus Preferred Qualifications...

Lugar: USA | 26/11/2025 18:11:02 PM | Salario: S/. $119600 - 179500 per year | Empresa: Northrop Grumman

DFT Engineer

tools (Modus and Genus) Well versed in JTAG/1500/1687 networks and BSDL, ICL and PDL knowledge Strong knowledge of logic...

Lugar: San Jose, CA | 20/11/2025 01:11:01 AM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Custom IP Design Engineer

with synthesis, physical design flows (Genus, Innovus or FusionCompiler) and STA timing closure (PrimeTime or Tempus). Knowledge...

Lugar: San Diego, CA | 01/11/2025 01:11:37 AM | Salario: S/. $115600 - 173400 per year | Empresa: Qualcomm