DMTS Digital Design Engineer / Chip Lead

/ Genus) and guide optimization for PPA targets across all design blocks. IP Management: Define interfaces between PHY... with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing analysis (PrimeTime or Tempus...

Lugar: Minneapolis, MN | 29/04/2026 20:04:05 PM | Salario: S/. No Especificado | Empresa: Micron

RTL Design Engineer

and/or VHDL o Synthesis tools (Design Compiler, Genus) o Scripting languages (Python, Perl, TCL) Preferred Qualifications...

Lugar: Austin, TX | 27/04/2026 02:04:35 AM | Salario: S/. No Especificado | Empresa: Intel

Digital Design Engineer

. Knowledge in EDA tools such as Cadence Digital EDA suite (Genus, Tempus, Jasper, Voltus, Modus, Conformal etc.) is an advantage...

Lugar: San Diego, CA | 17/04/2026 17:04:01 PM | Salario: S/. No Especificado | Empresa: Syntiant

Physical Design Engineer

process nodes (5nm and below) Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL...

Lugar: Austin, TX | 16/04/2026 21:04:02 PM | Salario: S/. $15000 - 27000 per year | Empresa: Etched

CPU Synthesis CAD Engineer

nodes (5nm or lower) Strong user of synthesis tools such as Cadence Genus or Synopsys Fusion Compiler Proven track record...

Lugar: Santa Clara, CA | 11/04/2026 18:04:10 PM | Salario: S/. No Especificado | Empresa: Qualcomm

Digital Flow Enablement Solutions Architect

and running Genus/Innovus to validate techLEF correctness and library performance and DRC correctness Tempus timing flow..., Liberate MX, Liberate AMS Simulators: Spectre, AMS, Xcelium Digital: Genus, Innovus, Tempus, Voltus, PrimeTime etc The...

Lugar: USA | 28/03/2026 03:03:28 AM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
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