Physical Design Engineer

process nodes (5nm and below) Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL...

Lugar: Austin, TX | 16/04/2026 21:04:19 PM | Salario: S/. $15000 - 27000 per year | Empresa: Etched

Staff Engineer, Digital Design Engineering (AI/ML)

, area, and power targets Perform synthesis with timing and placement constraints (Genus), static timing analysis and power..., BIST), and clock domain crossing methodologies Proficiency with Cadence digital design tools: Genus, Innovus, Tempus, Conformal...

Lugar: Chandler, AZ | 16/04/2026 18:04:15 PM | Salario: S/. No Especificado | Empresa: Analog Devices

CPU Synthesis CAD Engineer

nodes (5nm or lower) Strong user of synthesis tools such as Cadence Genus or Synopsys Fusion Compiler Proven track record...

Lugar: Santa Clara, CA | 12/04/2026 00:04:13 AM | Salario: S/. No Especificado | Empresa: Qualcomm

Digital Flow Enablement Solutions Architect

and running Genus/Innovus to validate techLEF correctness and library performance and DRC correctness Tempus timing flow..., Liberate MX, Liberate AMS Simulators: Spectre, AMS, Xcelium Digital: Genus, Innovus, Tempus, Voltus, PrimeTime etc The...

Lugar: USA | 28/03/2026 00:03:34 AM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
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