Lead ASIC Design Engineer
: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static...
Lugar: San Jose, CA | 20/06/2026 21:06:34 PM | Salario: S/. No Especificado | Empresa: Broadcom
Infra Systems Physical Architect
Sync Clock Routing Formal verification experience Power domain analysis experience Design Compiler/Fusion Compiler/Genus...
Lugar: San Diego, CA | 19/06/2026 23:06:20 PM | Salario: S/. No Especificado | Empresa: Qualcomm
Senior Physical Design Engineer for Core IP
Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus) Perform CPU level timing analysis...
Lugar: Hillsboro, OR | 19/06/2026 22:06:13 PM | Salario: S/. No Especificado | Empresa: Intel
GOLF COURSE SUPERINTENDENT NF4
¿ in its message. Ensures the attractiveness and constant readiness for play of the course. Determines the appropriate genus...
Lugar: Oceanside, CA | 19/06/2026 19:06:09 PM | Salario: S/. $34 - 37 per hour | Empresa: Federal government of the United States
Principal Product Engineer
products. Job responsibilities: Perform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis..., Performance & Area (PPA) for latest digital ASICs Understand the internal flow within the Genus for newly developed features...
Lugar: San Jose, CA | 16/06/2026 22:06:19 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
Senior Implementation Methodology Engineer
-and-route tools from Synopsys (DC/FC, ICC2, PrimeTime) and/or Cadence (Genus, Innovus, Tempus). Prior experience in data...
Lugar: Santa Clara, CA | 14/06/2026 00:06:20 AM | Salario: S/. No Especificado | Empresa: Nvidia
RTL2GDS, Principal AE
, and Logical Equivalence Checking Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus...
Lugar: San Jose, CA | 13/06/2026 18:06:36 PM | Salario: S/. $123200 - 228800 per year | Empresa: Cadence Design Systems
FPGA Engineer Engineer (eInfochips)
, Questa CDC, Fusion Compiler, Design Compiler, Genus. Proficiency with UPF (Low power intent) Proficiency in clock...
Lugar: San Jose, CA | 13/06/2026 18:06:04 PM | Salario: S/. No Especificado | Empresa: Arrow Electronics
Principal Engineer, Digital Design Engineer (AI/ML)
(Genus), STA and power analysis (Tempus), and logical equivalence checking (Conformal) Lead architecture and design reviews..., BIST), and clock domain crossing methodologies Proficiency with Cadence digital design tools: Genus, Innovus, Tempus, Conformal...
Lugar: Chandler, AZ | 13/06/2026 00:06:36 AM | Salario: S/. No Especificado | Empresa: Analog Devices
RTL2 GDS, Sr Principal AE
, and Logical Equivalence Checking Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus...
Lugar: USA | 12/06/2026 21:06:39 PM | Salario: S/. $126000 - 234000 per year | Empresa: Cadence Design Systems