Senior Design Verification Engineer

advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications.... Hardware Description Languages (HDL) such as Verilog or VHDL. Basic understanding of verification concepts (simulation...

Lugar: Sunnyvale, CA | 22/07/2026 23:07:14 PM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise

SoC Design Verification Engineer (2026 New College Graduate)

of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global... with HDL languages such as Verilog and SystemVerilog Experience with scripting languages like Python, Tcl/Tk, Perl...

Lugar: Texas | 21/07/2026 21:07:18 PM | Salario: S/. No Especificado | Empresa: GlobalFoundries

Embedded Engineer (Mid-Sr Levels)

and analytical skills. Highly motivated, well-organized self-starter. Desired Skills AMD/Xilinx FPGA HDL, hardware... design services. At Vanteon, we develop products for companies that range from small start-ups to large Fortune 50 companies...

Lugar: Pittsford, NY | 21/07/2026 17:07:41 PM | Salario: S/. $115000 - 150000 per year | Empresa: Vanteon Corporation

Embedded Engineer (Jr. Level)

development Linux BSP bring-up on custom hardware platforms FPGA HDL and block design familiarity Experience with Python... design services. At Vanteon, we develop products for companies that range from small start-ups to large Fortune 50 companies...

Lugar: Pittsford, NY | 21/07/2026 17:07:20 PM | Salario: S/. $80000 - 120000 per year | Empresa: Vanteon Corporation

Digital Signal Processing Engineer (Sr. Levels)

, including: MATLAB/Simulink, plus DSP Systems Toolbox (required) MathWorks HDL Coder (required) Mentor Graphics ModelSim..., Hardware, Software, and FPGA design services. At Vanteon, we develop products for companies that range from small start-ups...

Lugar: Pittsford, NY | 19/07/2026 17:07:30 PM | Salario: S/. $150000 - 175000 per year | Empresa: Vanteon Corporation

FPGA Design Engineer (MTD, San Jose, CA)

and cost-effectively. Together, companies deliver manufacturing automation across industries and applications around the world... Memory interfaces Experience with Altera/AMD FPGA tool flows Proficiency with Verilog HDL Language Familiarity with UVM...

Lugar: San Jose, CA | 18/07/2026 02:07:23 AM | Salario: S/. $135400 per year | Empresa: Teradyne

Senior FPGA Design Engineer (MTD, San Jose, CA)

and cost-effectively. Together, companies deliver manufacturing automation across industries and applications around the world... FPGA tool flows Proficiency with Verilog HDL Language Familiarity with UVM Methodology Scripting languages experience...

Lugar: San Jose, CA | 18/07/2026 00:07:35 AM | Salario: S/. No Especificado | Empresa: Teradyne

Senior FPGA Design Engineer (MTD, Tualatin, OR)

and cost-effectively. Together, companies deliver manufacturing automation across industries and applications around the world... FPGA tool flows Proficiency with Verilog HDL Language Familiarity with UVM Methodology Scripting languages experience...

Lugar: Tualatin, OR | 17/07/2026 21:07:19 PM | Salario: S/. No Especificado | Empresa: Teradyne

FPGA Design Engineer (MTD, Tualatin, OR)

and cost-effectively. Together, companies deliver manufacturing automation across industries and applications around the world... Memory interfaces Experience with Altera/AMD FPGA tool flows Proficiency with Verilog HDL Language Familiarity with UVM...

Lugar: Tualatin, OR | 17/07/2026 20:07:17 PM | Salario: S/. $123100 per year | Empresa: Teradyne