FPGA Design Engineer (MTD, San Jose, CA)

and cost-effectively. Together, companies deliver manufacturing automation across industries and applications around the world... Memory interfaces Experience with Altera/AMD FPGA tool flows Proficiency with Verilog HDL Language Familiarity with UVM...

Lugar: San Jose, CA | 17/07/2026 20:07:16 PM | Salario: S/. $135400 per year | Empresa: Teradyne

Senior FPGA Design Engineer (MTD, Tualatin, OR)

and cost-effectively. Together, companies deliver manufacturing automation across industries and applications around the world... FPGA tool flows Proficiency with Verilog HDL Language Familiarity with UVM Methodology Scripting languages experience...

Lugar: Tualatin, OR | 17/07/2026 19:07:36 PM | Salario: S/. No Especificado | Empresa: Teradyne

Staff FPGA Engineer, EW

with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies... processes. This will require expertise in HDL languages, FPGA architecture, and AMD/Xilinx development workflow...

Lugar: Costa Mesa, CA | 08/07/2026 02:07:23 AM | Salario: S/. No Especificado | Empresa: Anduril Industries

Staff Digital Hardware Engineer

with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies... throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library...

Lugar: Costa Mesa, CA | 07/07/2026 23:07:59 PM | Salario: S/. No Especificado | Empresa: Anduril Industries