Director, Design Verification

(SOCs), from architecture and design all the way through layout, packaging, prototype validation and production ramp up. The... both internal and external IPs and driving a high quality design tape-out for the CCS products. As part of SOC Design...

Lugar: Santa Clara, CA | 22/07/2026 22:07:29 PM | Salario: S/. No Especificado | Empresa: Marvell

Principal Analog Layout Engineer

development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs...) develops Marvell's most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Storage, Optics...

Lugar: San Diego, CA | 16/07/2026 22:07:15 PM | Salario: S/. $152300 - 225440 per year | Empresa: Marvell

Sr Staff Analog Layout Engineer

Engineering (CE) develops Marvell's most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Storage... algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating...

Lugar: San Diego, CA | 16/07/2026 18:07:24 PM | Salario: S/. $129100 - 191030 per year | Empresa: Marvell

Silicon Photonics TD Process/Product Integration Engineer

qualifications. Primary Responsibilities: A Process Integrator collaborates with Yield Analysis, Device and Defect Engineers, IPS... technical problems and deliver product milestones;interfacing between IPS, F11x process engineering, finance, planning, wafer...

Lugar: Albuquerque, NM | 27/06/2026 02:06:23 AM | Salario: S/. No Especificado | Empresa: Intel

Analog Engineer

, and implement analog circuits and mixed-signal IPs, including ADCs, DACs, voltage regulators, and high-speed I/O interfaces... state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology...

Lugar: Hillsboro, OR | 16/06/2026 23:06:25 PM | Salario: S/. No Especificado | Empresa: Intel

Senior Silicon Photonics TD Reliability Engineer

and collaborating with the SiPh fab process integration, Integrated Photonics Solutions (IPS) R&D design team, Foundry Q&R teams... while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the...

Lugar: Rio Rancho, NM | 08/06/2026 00:06:49 AM | Salario: S/. No Especificado | Empresa: Intel

Senior Principal Engineer, Chip Lead, Photonic Fabric Chiplet

into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging... Own the end‑to‑end product design spanning Electrical IC, Photonic IC, firmware stack, and advanced packaging design...

Lugar: Santa Clara, CA | 14/05/2026 18:05:28 PM | Salario: S/. No Especificado | Empresa: Marvell

Sr. Staff, Software Engineer - C++, C#, Python

development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs...) develops Marvell most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Automotive, Storage, Optics...

Lugar: Santa Clara, CA | 06/05/2026 18:05:59 PM | Salario: S/. $131010 - 196300 per year | Empresa: Marvell

Staff Software Engineer - C++, C#, Python

development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs...) develops Marvell most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Automotive, Storage, Optics...

Lugar: Santa Clara, CA | 06/05/2026 18:05:25 PM | Salario: S/. $111070 - 166400 per year | Empresa: Marvell

Senior Applications and Solutions Engineer - Foundry Services

by delivering cutting-edge silicon process and packaging technology leadership for the AI era. Intel Foundry will be differentiated... x86 cores, graphics, AI, and Arm/RISC-V IPs, world-class design services, and operationally resilient global manufacturing...

Lugar: Chandler, AZ | 06/05/2026 18:05:50 PM | Salario: S/. No Especificado | Empresa: Intel