Package Design Engineer

. Netlist management for heterogeneous chiplet assemblies using latest EDA solutions. Supporting activities related... packaging, chiplet architectures – co-design, layout, and netlist management. Knowledge of Signal and Power Integrity...

Lugar: Santa Clara, CA | 28/03/2026 00:03:57 AM | Salario: S/. $158600 - 234650 per year | Empresa: Marvell

Staff DFT Engineer

from RTL/netlist through post-silicon debug. In this role, you will partner closely with RTL, Physical Design, and ATE teams... DFT lifecycle experience, from RTL/netlist through silicon debug Strong debugging skills, attention to detail, and sense...

Lugar: Santa Clara, CA | 24/02/2026 19:02:39 PM | Salario: S/. $128000 - 189370 per year | Empresa: Marvell
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