STA Engineer

-to-Netlist and Netlist-to-Netlist). Understanding of SOC clocking and reset methodology and implementation. Scripting skills...

Lugar: Santa Clara, CA | 01/08/2026 02:08:55 AM | Salario: S/. $153200 - 229800 per year | Empresa: Qualcomm

HBM SoC Physical Design Engineer

logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers.... Required Qualifications Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs...

Lugar: Folsom, CA | 02/08/2026 02:08:57 AM | Salario: S/. $121000 - 205000 per year | Empresa: Micron

Senior Design Engineer

and synthesized netlist (gate level) verification at block, subsystem, and fullchip level Facilitate netlist bring up to achieve...

Lugar: San Jose, CA | 07/08/2026 21:08:18 PM | Salario: S/. $116000 - 198000 per year | Empresa: Micron

Senior Design Engineer

best known design and verification practices and communicate them to the department Perform RTL and synthesized netlist (gate... level) verification at block, subsystem, and fullchip level Facilitate netlist bring up to achieve basic functionality...

Lugar: San Jose, CA | 13/07/2026 20:07:01 PM | Salario: S/. $116000 - 198000 per year | Empresa: Micron

Physical Design Engineer

technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform...

Lugar: Mountain View, CA | 14/08/2026 01:08:04 AM | Salario: S/. $100000 - 180000 per year | Empresa: Wipro