to develop and own complex SDC timing constraints for large hierarchical system-on-chip designs with multiple clock domains..., and voltage and temperature conditions. Develop, maintain, and validate comprehensive Synopsys Design Constraints (SDC...
integration, and post-silicon validation. Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform... with power intent formats such as UPF or CPF and power-aware verification flows Experience writing and debugging SDC timing...
requirements. Key Responsibilities Designs and manages project plans for SRF and EC-SDC programs, including tracking..., and coordination related to water infrastructure funding programs, including SRF and EC-SDC projects. The position requires...
logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers...) across multi-mode/multi-corner (MMMC) scenarios;partner with RTL, architecture, and STA/signoff to converge designs. Integrate...
across complex AMD SoC designs, ensuring correctness across use cases and configurations Build and maintain automation... flows, including SystemVerilog, UPF, SDC timing constraints, and static analysis tools (e.g., Lint, CDC, RDC, LEC, VCLP/CLP...
margins, guard-bands, and sign-off criteria for advanced node designs. Managing complexities at 7nm, 5nm, and 3nm nodes..., including variation-aware timing (AOCV/POCV), crosstalk, and clock distribution. Developing and reviewing SDC constraints...
with hardware engineers on FPGA/SoC PCB board designs. Experience writing timing constraints (SDC) to achieve timing closure... on high-speed FPGA designs. Familiarity with common communication protocols (SPI, I2C, AXI, Avalon, Ethernet, AMBA, Wishbone...
). Ability to collaborate with hardware engineers on FPGA/SoC PCB board designs. Experience writing timing constraints (SDC...) to achieve timing closure on high-speed FPGA designs. Familiarity with common communication protocols (SPI, I2C, AXI, Avalon...
, including development of automation and scripts to support these flows · Develop timing constraints (SDC) ensuring correctness... · Ensure designs meet timing, power, and integration requirements prior to tapeout · Support final integration, signoff...
and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency..., and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging...