. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing closure across multiple corners and modes.... Analyze and resolve setup, hold, transition, capacitance, and noise violations. Develop and maintain timing constraints (SDC...
Description: At Steven Douglas Corp (SDC), we specialize in designing and building custom automated machines... build custom project. Machines do not cooperate on schedule, vendors miss, designs need re-work, software needs revamped...
Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs...-off for complex ASIC and SoC designs. Drive scan architecture, scan insertion, scan chain stitching, and scan compression...
synthesis flow (Design Compiler or Genus) and drive timing closure Define and maintain SDC timing constraints Review all RTL... for processor, CPU, DSP, or datapath-intensive designs Experience delivering at least one silicon tapeout through GDSII handoff...
logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers...) across multi-mode/multi-corner (MMMC) scenarios;partner with RTL, architecture, and STA/signoff to converge designs. Integrate...
Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration..., on-chip variation, signal integrity, and power-aware timing. Proven ability to develop and manage complex hierarchical SDC...
ever. You will drive physical implementation of advanced high‑bandwidth memory (HBM) system‑on‑chip (SoC) logic and base die designs..., clocking concepts, and Synopsys Design Constraints (SDC). Working knowledge of power intent methodologies including Unified...
to develop and own complex SDC timing constraints for large hierarchical system-on-chip designs with multiple clock domains..., and voltage and temperature conditions. Develop, maintain, and validate comprehensive Synopsys Design Constraints (SDC...
logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers...) across multi-mode/multi-corner (MMMC) scenarios;partner with RTL, architecture, and STA/signoff to converge designs. Integrate...
across complex AMD SoC designs, ensuring correctness across use cases and configurations Build and maintain automation... flows, including SystemVerilog, UPF, SDC timing constraints, and static analysis tools (e.g., Lint, CDC, RDC, LEC, VCLP/CLP...