ASIC/SoC Design Engineer, RTL design for SoC IPs

validation. Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform static timing analysis (STA... → Synthesis → STA → Physical Design → Tape-out Experience writing and debugging SDC timing constraints, including multi-cycle...

Lugar: San Jose, CA | 21/02/2026 02:02:19 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Bridge Engineer

on you to: Prepare Bridge designs following Caltrans PS&E process. Work on projects that typically include bridge (steel plate girder... (SDC) Qualifications Required Qualifications Bachelor's degree Previous experience in bridge design Requires...

Lugar: California | 30/01/2026 22:01:14 PM | Salario: S/. No Especificado | Empresa: HDR