Principal/ Senior Principal Digital ASIC Circuit Design Engineer

or Cadence Tempus Candidate must be a US Citizen and have the ability to obtain/ maintain a security clearance once on board..., Cadence Genus or Cadence RTL Compiler - Static Timing – Synopsys Primetime or Cadence Tempus Preferred Qualifications...

Lugar: USA | 26/11/2025 18:11:16 PM | Salario: S/. $119600 - 179500 per year | Empresa: Northrop Grumman

ASIC Methodology Engineer

., PrimeTime and Tempus Problem-solving and analytical mindset Preferred Qualifications: Critical thinking with good software...

Lugar: San Diego, CA | 25/11/2025 20:11:22 PM | Salario: S/. $115600 - 173400 per year | Empresa: Qualcomm

CPU Physical Design Timing Engineer (Austin, TX)

. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA... environment. Familiar with digital flow design implementation RTL to GDS : ICC, Innovus , PT/Tempus Minimum Qualifications...

Lugar: Austin, TX | 22/11/2025 02:11:35 AM | Salario: S/. $122500 - 183700 per year | Empresa: Qualcomm

IP Integration Engineer

with Cadence Innovus or equivalent toolset Experience in reading timing reports from static timing tools such as Tempus...

Lugar: Fort Collins, CO | 21/11/2025 00:11:10 AM | Salario: S/. $91000 - 146000 per year | Empresa: Broadcom

Senior Timing Methodology Engineer

. What You'll Be Doing: Improve and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow... and beyond. Expertise in coding- TCL, Python. C++ is a plus. Familiarity with industry standard ASIC tools: PT, ICC, Redhawk, Tempus...

Lugar: Santa Clara, CA | 20/11/2025 00:11:59 AM | Salario: S/. No Especificado | Empresa: Nvidia