Principal/ Senior Principal Digital ASIC Circuit Design Engineer

or Cadence Tempus Candidate must be a US Citizen and have the ability to obtain/ maintain a security clearance once on board..., Cadence Genus or Cadence RTL Compiler - Static Timing – Synopsys Primetime or Cadence Tempus Preferred Qualifications...

Lugar: USA | 26/11/2025 18:11:51 PM | Salario: S/. $119600 - 179500 per year | Empresa: Northrop Grumman

ASIC Methodology Engineer

., PrimeTime and Tempus Problem-solving and analytical mindset Preferred Qualifications: Critical thinking with good software...

Lugar: San Diego, CA | 25/11/2025 22:11:04 PM | Salario: S/. $115600 - 173400 per year | Empresa: Qualcomm

CPU Physical Design Timing Engineer (Austin, TX)

. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA... environment. Familiar with digital flow design implementation RTL to GDS : ICC, Innovus , PT/Tempus Minimum Qualifications...

Lugar: Austin, TX | 21/11/2025 19:11:01 PM | Salario: S/. $122500 - 183700 per year | Empresa: Qualcomm