CPU Design Timing Engineer
such as CPUs or other similar designs Experience in a static timing analysis tool such as PrimeTime®/Tempus® Knowledge...
Lugar: Santa Clara, CA | 29/10/2025 00:10:19 AM | Salario: S/. No Especificado | Empresa: Apple
CPU Design Timing Engineer
with a static timing analysis tool such as PrimeTime® or Tempus® Experience with timing analysis with multiple clock and power...
Lugar: Santa Clara, CA | 28/10/2025 20:10:54 PM | Salario: S/. No Especificado | Empresa: Apple
Senior Timing CAD Engineer, Applied AI
, Nanotime, Tempus) to perform multi-corner, multi-mode optimization and constraint debugging. Implement scalable orchestration... engineering data. Working knowledge of timing tools (PrimeTime, Nanotime, Tempus) and scripting integration with EDA...
Lugar: Santa Clara, CA | 23/10/2025 23:10:20 PM | Salario: S/. No Especificado | Empresa: Nvidia
CAD Engineer, Silicon Learning and Static Timing Analysis
timing analysis, DFT, physical design, failure analysis or CAD Static Timing Analysis with Primetime, Tempus, or equivalent...
Lugar: Austin, TX | 22/10/2025 02:10:58 AM | Salario: S/. No Especificado | Empresa: Apple
CAD Engineer, Silicon Learning and Static Timing Analysis
in static timing analysis, DFT, physical design, failure analysis or CAD Static Timing Analysis with Primetime, Tempus...
Lugar: Austin, TX | 21/10/2025 18:10:33 PM | Salario: S/. No Especificado | Empresa: Apple
HW SOC/ASIC Physical Design Engineer, Staff/Sr Staff (US Citizenship Required)
(STA) using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop, validate, and maintain timing...
Lugar: San Diego, CA | 19/10/2025 01:10:05 AM | Salario: S/. No Especificado | Empresa: Qualcomm
Signoff Static Timing Analysis CAD Engineer
of Cadence tempus STA tool, or of the timing engines of synthesis and place and route tools. Principal Duties...
Lugar: San Diego, CA | 19/10/2025 01:10:13 AM | Salario: S/. $98500 - 147700 per year | Empresa: Qualcomm
HW SOC/ASIC Physical Design Engineer, Senior (US Citizenship Required)
-level static timing analysis (STA) using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop...
Lugar: San Diego, CA | 18/10/2025 21:10:27 PM | Salario: S/. $115600 - 173400 per year | Empresa: Qualcomm
IC Physical Design Lead AE
Equivalence Checking Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2...
Lugar: San Jose, CA | 17/10/2025 00:10:17 AM | Salario: S/. $102900 - 191100 per year | Empresa: Cadence Design Systems
Custom Logic Design & STA Engineer
, and Tempus. Experience in analog/mixed-signal circuit design from architecture to fundamental implementation. Experience...
Lugar: Cupertino, CA | 16/10/2025 22:10:27 PM | Salario: S/. No Especificado | Empresa: Apple