Verification Engineer

. Tasks Build cocotb-based testbenches for RTL blocks ranging from complicated datapaths to multilevel interconnect, driven... violations directly in simulation, plus cover property statements to close functional-coverage gaps. Cross-check RTL behavior...

Lugar: Karlsruhe, Baden-Württemberg | 24/09/2026 17:09:56 PM | Salario: S/. No Especificado | Empresa: Ubitium GmbH

Senior Digital ASIC Design Engineer Synthesis (m/f/d)

and at scale. Job Duties & Responsibilities Architecture development for CMOS designs Design and RTL coding of digital and full... development cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard...

Lugar: Baden-Württemberg | 24/09/2026 17:09:42 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior Digital ASIC Design Engineer Verification (m/f/d)

Architecture development for CMOS designs Design and RTL coding of digital and full-custom modules Verification on module and chip... design (SOC), ASIC design methodologies and silicon development cycle Experience in Register Transfer Level (RTL) coding...

Lugar: Baden-Württemberg | 24/09/2026 17:09:46 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior Engineer, FPGA, MEO 1

and hardware specifications through RTL design, optimising for silicon area, performance, and power. Design and implement digital..., and testing DSP algorithms in RTL code. Hands-on experience with Xilinx FPGA platforms (RFSoC, Versal Gen1/Gen2). Expertise...

Lugar: Betzdorf, Rheinland-Pfalz | 18/09/2026 22:09:16 PM | Salario: S/. No Especificado | Empresa: SES S.A.

Senior Engineer, FPGA, MEO 1

and hardware specifications through RTL design, optimising for silicon area, performance, and power. Design and implement digital..., and testing DSP algorithms in RTL code. Hands-on experience with Xilinx FPGA platforms (RFSoC, Versal Gen1/Gen2). Expertise...

Lugar: Betzdorf, Rheinland-Pfalz | 18/09/2026 17:09:58 PM | Salario: S/. No Especificado | Empresa: SES