Senior Engineer, FPGA, MEO 1

and hardware specifications through RTL design, optimising for silicon area, performance, and power. Design and implement digital..., and testing DSP algorithms in RTL code. Hands-on experience with Xilinx FPGA platforms (RFSoC, Versal Gen1/Gen2). Expertise...

Lugar: Betzdorf, Rheinland-Pfalz | 18/09/2026 17:09:28 PM | Salario: S/. No Especificado | Empresa: SES

Senior Engineer Digital IP (f/m/div)

. Are you in? Your role Key responsibilities in your new role Hands-on digital IP design execution, RTL implementation, design documentation..., integration support, and release readiness. Develop high-quality RTL in System Verilog/Verilog for reusable, configurable...

Lugar: Dresden, Sachsen | 09/09/2026 01:09:37 AM | Salario: S/. No Especificado | Empresa: Infineon

Senior Engineer Digital IP (f/m/div)

. Are you in? Your role Key responsibilities in your new role Hands-on digital IP design execution, RTL implementation, design documentation..., integration support, and release readiness. Develop high-quality RTL in System Verilog/Verilog for reusable, configurable...

Lugar: Dresden, Sachsen | 01/09/2026 22:09:15 PM | Salario: S/. No Especificado | Empresa: Infineon