CPU Pre-Silicon Verification Engineer

scalable UVM‑based (or similar) constrained‑random verification environments, including reusable testbenches, agents, sequences... developing UVM-based testbenches for reusable and scalable verification environments. Define and implement validation strategies...

Lugar: Guadalajara, Jal. | 24/01/2026 18:01:38 PM | Salario: S/. No Especificado | Empresa: Intel
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