SoC Pre-Silicon Verification Engineer

-standard verification methodologies such as UVM or System Verilog or Digital Design Advance English level... Qualifications: 3+ years System Verilog and UVM experience 2+ years in: Python for test automation. Simulation tools (VCS...

Lugar: Guadalajara, Jal. | 11/05/2026 02:05:31 AM | Salario: S/. No Especificado | Empresa: Intel