Sr. Principal Digital Signal Processing Engineer

partners We are seeking cleared or clearable Sr. Principal Digital Signal Processing Engineers who are self-motivated... Signal Processing algorithms both in time and frequency domains, understanding of Digital Communication Systems and various...

Lugar: Cincinnati, OH | 22/07/2026 17:07:17 PM | Salario: S/. No Especificado | Empresa: Northrop Grumman

Sr. FPGA Modem and Physical Layer Development Engineer, Amazon Leo

, and simulation validation. System Integration: Collaborate with Digital Communications and RF system architects to implement complex... System Verilog/Verilog/VHDL. - Hands-on experience with Xilinx/AMD or Intel/Altera FPGAs Preferred Qualifications...

Lugar: Austin, TX | 21/07/2026 19:07:13 PM | Salario: S/. No Especificado | Empresa: Amazon

Lead FPGA Design Engineer

: Lead debugging and testing campaigns on physical printed circuit boards (PCBs) using lab equipment like digital... health, and resolution plans clearly to leadership, customers, and cross-functional stakeholders. JOB QUALIFICATIONS...

Lugar: Austin, TX | 18/07/2026 02:07:04 AM | Salario: S/. No Especificado | Empresa: Jabil

Sr Implementation Consultant

solutions. At the intersection of technology and the human experience, AlteraDigitalHealth is driving a new era of healthcare...Altera, a member of the N. Harris Computer Corporation family, delivers health IT solutions that support caregivers...

Lugar: New Jersey | 18/07/2026 01:07:14 AM | Salario: S/. $75000 - 85000 per year | Empresa: Harris Computer

FPGA Design Engineer (MTD, San Jose, CA)

supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge... with a minimum of 3 years of relevant work experience. Experience with Digital Design and Architecture RTL coding, synthesis...

Lugar: San Jose, CA | 17/07/2026 21:07:06 PM | Salario: S/. $135400 per year | Empresa: Teradyne

FPGA Engineering Manager (MTD, Tualatin, OR)

supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge... in Digital ASIC or FPGA design Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through...

Lugar: Tualatin, OR | 17/07/2026 19:07:04 PM | Salario: S/. No Especificado | Empresa: Teradyne

FPGA Design Engineer (MTD, Tualatin, OR)

supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge... with a minimum of 3 years of relevant work experience. Experience with Digital Design and Architecture RTL coding, synthesis...

Lugar: Tualatin, OR | 17/07/2026 18:07:18 PM | Salario: S/. $123100 per year | Empresa: Teradyne

FPGA Engineering Manager (MTD, San Jose, CA)

supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge... in Digital ASIC or FPGA design Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through...

Lugar: San Jose, CA | 17/07/2026 18:07:34 PM | Salario: S/. No Especificado | Empresa: Teradyne

FPGA Design Engineer

. Perform synchronous digital design, ensuring robust timing closure across complex, high-speed designs. Use Vivado and Vitis.../Microsemi/Actel, Intel/Altera, and Lattice devices. Apply Tcl scripting to automate design flows, tool configurations...

Lugar: Indialantic, FL | 16/07/2026 17:07:21 PM | Salario: S/. $50 - 80 per hour | Empresa: Actalent