IP Enablement Application Engineer

in SOC IP Integration 3+ years of combined experience in RTL design and DFT using Verilog/System Verilog Experience in ASIC...), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating...

Lugar: Chandler, AZ | 10/01/2026 19:01:48 PM | Salario: S/. No Especificado | Empresa: Intel

DFT Application Engineer

and guidance on DFT implementation strategies DFT Methodology & Quality Leadership Drive quality improvements in ASIC DFT/DFM... CMOS processes (22nm and below) 3+ years of combined experience in the following: implementing ASIC DFT/DFM insertion...

Lugar: Chandler, AZ | 10/01/2026 19:01:59 PM | Salario: S/. No Especificado | Empresa: Intel

Optical Engineer, Senior Staff

integrated component platforms with high speed Silicon photonics, transmit and receive amplifiers, controller ASIC’s with Marvell...

Lugar: Santa Clara, CA | 09/01/2026 00:01:24 AM | Salario: S/. $130740 - 195800 per year | Empresa: Marvell

Principal CAD Engineer

of hands-on experience in CAD flow development for ASIC and Custom designs preferred Experience with 12nm or below tape out...

Lugar: Santa Clara, CA | 08/01/2026 18:01:13 PM | Salario: S/. $146850 - 220000 per year | Empresa: Marvell

Senior Principal Hardware Validation

group designs and develops test platforms for validating multi-core Arm-based Network processors and custom ASIC’s, used... on protocols, validation workflows, and issue triage. Partner with SoC/ASIC, PHY, Firmware/Software, Diagnostics, System...

Lugar: Santa Clara, CA | 08/01/2026 03:01:49 AM | Salario: S/. $164650 - 246700 per year | Empresa: Marvell