Senior ASIC Integration and CAD Engineer

Integration and CAD Engineer, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet... - MSEE preferred Minimum 5 years experience in ASIC integration and front end design Demonstrated success in taking ASICs...

Lugar: Santa Clara, CA | 22/12/2024 18:12:52 PM | Salario: S/. $120000 - 193500 per year | Empresa: Palo Alto Networks

ASIC Analog Design Engineer II

, Oregon. You will design innovative CMOS, BiCMOS, and HBT Analog/Mixed Signal ASICs for our next-generation products.... Key Responsibilities: Design building blocks of next-generation ASICs using advanced ASIC tools. Run simulations...

Lugar: Beaverton, OR | 22/12/2024 18:12:13 PM | Salario: S/. No Especificado | Empresa: Fortive

Senior ASIC Integration and CAD Engineer

Integration and CAD Engineer, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet... - MSEE preferred Minimum 5 years experience in ASIC integration and front end design Demonstrated success in taking ASICs...

Lugar: Santa Clara, CA | 22/12/2024 02:12:23 AM | Salario: S/. $120000 - 193500 per year | Empresa: Palo Alto Networks

Electrical Engineer II - ASIC/FPGA (Onsite)

, implementation, verification, and integration of a wide variety of high-performance digital ASICs and FPGAs applied to signal.... You will get to work with cutting edge technologies developed both in house and by external vendors. You will learn how ASICs...

Lugar: Cedar Rapids, IA | 21/12/2024 23:12:26 PM | Salario: S/. $64000 - 128000 per year | Empresa: Raytheon Technologies

ASIC Design Engineer

Responsibilities · Control subsystem development in large mixed signal ASICs · Work with system architect to define control plane...

Lugar: San Jose, CA | 19/12/2024 18:12:19 PM | Salario: S/. No Especificado | Empresa: Infinera

ASIC Technical Lead

by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Development... of high-performance designs/ASICs from specification to tape-out. Arch/micro-architectural definition and writing arch/micro...

Lugar: San Jose, CA | 18/12/2024 18:12:09 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

ASIC Principal Engineer

by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Development... of high-performance designs/ASICs from specification to tape-out Arch/micro-architectural definition and writing arch/micro...

Lugar: San Jose, CA | 18/12/2024 18:12:45 PM | Salario: S/. No Especificado | Empresa: Cisco Systems