for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being... correctness of features. Supports SoC customers to ensure high quality integration of the IP block. Qualifications...
Lugar:
Folsom, CA | 29/05/2026 21:05:00 PM | Salario: S/. No Especificado | Empresa:
Intel into a code review where you give thoughtful feedback to an SDE1 on a Lambda function. You spend a focused block writing...
Lugar:
Seattle, WA | 29/05/2026 21:05:23 PM | Salario: S/. No Especificado | Empresa:
Amazon in Synthesis of a digital logic block or partition. At least 1 Completion of Tape Out on advanced technologies. 4+ years... requirements. Experience generating and verifying timing constraints while addressing timing violations at the chip or block level...
Lugar:
Austin, TX | 29/05/2026 21:05:01 PM | Salario: S/. No Especificado | Empresa:
IntelDescription Join the team that powers one of AWS's most critical services - Elastic Block Store (EBS)! The EBS...
Lugar:
Seattle, WA | 29/05/2026 19:05:56 PM | Salario: S/. No Especificado | Empresa:
Amazon in Synthesis of a digital logic block or partition. 2+ years of experience in each of the following: Experience with integrated... constraints while addressing timing violations at the chip or block level for CPU cores. Experience working closely with the...
Lugar:
Austin, TX | 29/05/2026 18:05:31 PM | Salario: S/. No Especificado | Empresa:
Intel in Synthesis of a digital logic block or partition. 1+ years of experience in each of the following: Experience with integrated... constraints while addressing timing violations at the chip or block level for CPU cores. Experience working closely with the...
Lugar:
Austin, TX | 29/05/2026 18:05:21 PM | Salario: S/. $105650 - 172860 per year | Empresa:
Intel, both independently and cross-functionally Serve as the software expert on a block or portion of the design, owning SW architecture...
FinFET process nodes. Working from SerDes standards to block specifications, you quickly identify potential circuit... Tracking and reviewing the work of sub-block owners Review SerDes standards and architecture documents to develop analog...
with design verification teams to review test plans and execution of test, ability to bring up block tests on silicon during lab... testing, and maintenance of designed blocks and reusable IPs. Produce comprehensive block uArchitecture and register Specs...
will have a strong background in timing constraints development, STA Signoff/Margins flows & methodologies for both SOC level and block level...
Lugar:
San Diego, CA | 29/05/2026 02:05:47 AM | Salario: S/. $115200 - 170390 per year | Empresa:
Marvell