Sr. STA Engineer

owners and block teams to resolve cross-boundary timing issues. Provide infrastructure and tooling support to timing owners...

Lugar: USA | 15/01/2026 18:01:05 PM | Salario: S/. No Especificado | Empresa: Intel

DFT Application Engineer

and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations... (MBIST, LBIST, SCAN, JTAG) at both ASIC design block level and full chip level, including ATPG validation and DFT timing...

Lugar: Chandler, AZ | 10/01/2026 23:01:07 PM | Salario: S/. No Especificado | Empresa: Intel