SENIOR SILICON DESIGN ENGINEER
, calibre and Prime Time. Experience in automated design flows for clock tree synthesis, clock gating techniques, buffer...
, calibre and Prime Time. Experience in automated design flows for clock tree synthesis, clock gating techniques, buffer...
, calibre and Prime Time. Experience in automated design flows for clock tree synthesis, clock gating techniques, buffer...
of layout synthesis and place and route techniques Experience with LVS and DRC tools such as Calibre Utilize AI-Enabled tools...
(fin quantization, degraded gm/gds, 3D RC extraction). EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX...
(fin quantization, degraded gm/gds, 3D RC extraction). EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX...
using industry-standard tools (Pegasus, Calibre, etc.) Contribute to chip-level planning including top-level floor planning..., and power/ground grid design Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools...
industry-standard verification engines (such as Calibre or ICV), with a proven ability to solve complex, systemic layout errors...
like Cadence (e.g., Innovus, , Tempus, Voltus, Pegasus, Calibre). Technical Concepts: Expertise in physically aware synthesis...
like Cadence (e.g., Innovus, , Tempus, Voltus, Pegasus, Calibre). Technical Concepts: Expertise in physically aware synthesis...
(Cadence Virtuoso Layout and Schematic Editor, Calibre, Hspice etc.) Experience with Design Rule Characterization...