Junior / Senior / Principal Design Validation & Test (DVT) Engineer roles Irvine, CA About The Role Celero..., communications, data center, AI, or high-performance computing products. Strong understanding of silicon debug methodologies...
Principal Full-Chip Physical Verification Engineer Key Responsibilities Team & Project Leadership Lead full chip Physical Verification effort Own execution plans, schedules for full-chip Drive accountability for quality, milestones, a...
Principal Full-Chip Physical Verification Engineer Key Responsibilities Team & Project Leadership Lead full chip Physical Verification effort Own execution plans, schedules for full-chip Drive accountability for quality, milestones, a...
Principal Full-Chip Physical Verification Engineer Key Responsibilities Team & Project Leadership Lead full chip Physical Verification effort Own execution plans, schedules for full-chip Drive accountability for quality, milestones, a...
Principal Product Engineer About the Job CeleroCommunications is building next‑generation coherent DSP integrated... to drive the transition of Celero’s products from development into qualified, high‑yield, high‑volume manufacturing...
Principal Product Engineer About the Job CeleroCommunications is building next‑generation coherent DSP integrated... to drive the transition of Celero’s products from development into qualified, high‑yield, high‑volume manufacturing...
CeleroCommunications ( ) is building the next generation of intelligent optical connectivity for AI infrastructure. Founded...Director of Product Marketing – Coherent DSP & Optical Networking Location: Irvine, CA (HQ) or remote About Celero...
Principal Physical Design Engineer Core Responsibilities RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. Design Optimization: Manage floor-planning, bump planning, power grid des...
Principal High-Speed Analog Layout Design Engineer About the Role Celero Communication Inc. is an exciting and fast... are valued The opportunity to grow alongside Celero as we scale and shape the future of our industry A foundational role...
Principal Physical Design Engineer Core Responsibilities RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. Design Optimization: Manage floor-planning, bump planning, power grid des...