Senior Circuit Design Engineer

. If you are looking for a challenging and exciting role in improving the netlist and timing quality of our designs and if you are a self-starter and highly...

Lugar: Santa Clara, CA | 29/01/2026 03:01:36 AM | Salario: S/. No Especificado | Empresa: Nvidia

Senior ASIC RTL Integration and Netlisting Engineer

, and/or full chip level Drive RTL integration, synthesis, along with all physical netlist deliverables across various milestones... Drive formal equivalence checking, netlist quality checks, asynchronous checking including clock domain crossing checks...

Lugar: Santa Clara, CA | 24/01/2026 18:01:28 PM | Salario: S/. No Especificado | Empresa: Nvidia

Sr. Physical Design Engineer

timing constraints. - Check the RTL design for clean synthesis run, perform STA and LEC on netlist. - Work with RFIC teams...

Lugar: San Diego, CA | 17/01/2026 22:01:16 PM | Salario: S/. No Especificado | Empresa: Amazon

Senior ASIC Physical Design Engineer, Netlisting

-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects... such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist...

Lugar: Santa Clara, CA | 08/01/2026 23:01:51 PM | Salario: S/. No Especificado | Empresa: Nvidia

IC DESIGN ENGINEER

implementing chips from netlist to GDSii with good understanding of the technology elements as well as design flow in all stages...

Lugar: San Jose, CA | 18/12/2025 23:12:32 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom
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