Senior ASIC Physical Design Engineer, Netlisting

-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects... such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist...

Lugar: Santa Clara, CA | 08/01/2026 19:01:03 PM | Salario: S/. No Especificado | Empresa: Nvidia

IC DESIGN ENGINEER

implementing chips from netlist to GDSii with good understanding of the technology elements as well as design flow in all stages...

Lugar: San Jose, CA | 18/12/2025 18:12:46 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

ASIC Design Engineer Staff

of our fast-paced chip design group, you will become an expert in building high-speed ASICs, from specifications to final netlist... skills in leading and implementing high performance modules from specification to final netlist. Knowledge of Computer...

Lugar: Sunnyvale, CA | 13/12/2025 21:12:49 PM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise

DFM Valor Engineer

Qualifications: Experience with scripting for automation (VBScript, Python). Familiarity with other EDA tools and basic netlist...

Lugar: Irvine, CA - Palo Alto, CA | 05/12/2025 22:12:36 PM | Salario: S/. No Especificado | Empresa: Rivian

Senior Staff Physical Design Manager

in lieu of a formal degree Must have a background in ASIC or SOC development Physical design knowledge, from netlist... of ASIC or SOC Netlist to GDS tape-out Experience as either top-level physical design lead, STA chip Lead or chip DFT lead...

Lugar: Santa Clara, CA | 21/11/2025 03:11:58 AM | Salario: S/. $157170 - 235400 per year | Empresa: Marvell