CAD and PPA Methodology Engineer

tools · Design constraint management for power, timing, clocking, interfaces · Formal Verification for RTL-netlist... and netlist-netlist checks · Clock Tree Analysis and Optimization · ECO methods for functional and timing fixes · Managing...

Lugar: San Diego, CA | 03/03/2026 03:03:58 AM | Salario: S/. $161800 - 242600 per year | Empresa: Qualcomm

Human Resources Assistant

Human Resources Assistant Company Overview: Netlist Inc. (NASDAQ: NLST) is a leading provider of high-performance...

Lugar: Irvine, CA | 24/03/2026 18:03:45 PM | Salario: S/. $25 - 30 per hour | Empresa: Netlist

ASIC Senior Design Engineer

, from specifications to final netlist. We give you opportunities to work on complex blocks where you can challenge yourself and grow... from specification to final netlist. · Knowledge of Computer Architecture/networking protocols through prior work is strongly desired...

Lugar: Roseville, CA | 04/04/2026 17:04:59 PM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise

Design Engineer

in 2nm/3nm/5nm technology nodes . The person should have hands on experience on netlist- gds implementation of multimillion...

Lugar: San Jose, CA | 26/03/2026 03:03:14 AM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

HBM SoC Physical Design Engineer

logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers... from netlist to GDSII on advanced nodes and complex designs. Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus...

Lugar: Richardson, TX | 26/03/2026 02:03:58 AM | Salario: S/. No Especificado | Empresa: Micron

Staff Design Engineer

and verification practices and communicate them to the department Perform RTL and synthesized netlist (gate level) verification... at block, subsystem, and full chip level Facilitate netlist bring up to achieve basic functionality Responsible...

Lugar: San Jose, CA | 26/03/2026 00:03:28 AM | Salario: S/. $116000 - 246000 per year | Empresa: Micron

Digital Design Engineer

and effective chip layout. Convert RTL code into a gate-level netlist, ensuring the design meets area, power, and performance...

Lugar: Pasadena, CA | 24/03/2026 18:03:06 PM | Salario: S/. $100000 per year | Empresa: AMETEK

Senior Design Engineer

best known design and verification practices and communicate them to the department Perform RTL and synthesized netlist (gate... level) verification at block, subsystem, and fullchip level Facilitate netlist bring up to achieve basic functionality...

Lugar: San Jose, CA | 22/03/2026 03:03:41 AM | Salario: S/. $93000 - 198000 per year | Empresa: Micron