FPGA/ASIC Design Engineer
networking protocols (Ethernet, PCI-Express, USB) Expertise in synthesis, static timing analysis, and timing closure (Synopsys...
networking protocols (Ethernet, PCI-Express, USB) Expertise in synthesis, static timing analysis, and timing closure (Synopsys...
: Simulator (Synopsys VCS or Cadence Xcelium or Siemens Questasim or equivalent tools), debugging tools (Synopsys Verdi or Cadence...
experience Preferred Skills & Qualifications Experience with Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence...
Experience and knowledge of EDA tools: Simulator (Synopsys VCS or Cadence Xcelium or Siemens Questasim or equivalent tools...), debugging tools (Synopsys Verdi or Cadence Simvision). Job Details: Job Type: Contract Pay Rate: $90 - $100 an hour...
IP blocks across multi-site environments. EDA & Debug: Extensive experience with Synopsys VCS and Verdi for logic...
with Cadence or Synopsys tools. Deep expertise in SDC constraint writing, clock gating, and hierarchical synthesis. Familiarity...
with Cadence or Synopsys tools. Deep expertise in SDC constraint writing, clock gating, and hierarchical synthesis. Familiarity...
with Cadence or Synopsys tools. Deep expertise in SDC constraint writing, clock gating, and hierarchical synthesis. Familiarity...
with Cadence or Synopsys tools. Deep expertise in SDC constraint writing, clock gating, and hierarchical synthesis. Familiarity...
with Cadence or Synopsys tools. Deep expertise in SDC constraint writing, clock gating, and hierarchical synthesis. Familiarity...